Resetting 2-Order Sigma –Delta Modulator in130 nm CMOS Technology

In current scenario highresolutionADC architecture based on a resetting modulator required high gain operational Transcoductace Amplifier (OTA)and quanitizerin low-voltage nanometer-scale CMOSprocesses because of good speed and calibration-free response are becoming more popular in communication system. Proposed work achieves such high resolution, despite poor component matching using Folded cascodeOTA and two different 1bit and 1.5 bit quantizerwithswiched capacitor Modulator design toreduced thermal noise and a possible optimization of power consumption.Above Quantizeris& OTA in Resetting modulator designed and simulated using H-SPICE having very low power consumptionin 130nm TSMC CMOS technology. Index Terms :ADC, high-resolution, Resetting ∑∆ modulator,Quantizer,Comparator,D flipflop.